qick.drivers.tproc
Drivers for the QICK timed processor (tProc).
Classes
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AxisTProc64x32_x8 class |
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Axis_QICK_Proc class |
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Axis_QICK_Proc class |
- class qick.drivers.tproc.AxisTProc64x32_x8(*args: Any, **kwargs: Any)[source]
Bases:
SocIpAxisTProc64x32_x8 class
AXIS tProcessor registers: START_SRC_REG * 0 : internal start (using START_REG) * 1 : external start (using “start” input)
Regardless of the START_SRC, the start logic triggers on a rising edge: A low level arms the trigger (transitions from “end” to “init” state). A high level fires the trigger (starts the program). To stop a running program, see reset().
START_REG * 0 : init * 1 : start
MEM_MODE_REG * 0 : AXIS Read (from memory to m0_axis) * 1 : AXIS Write (from s0_axis to memory)
MEM_START_REG * 0 : Stop. * 1 : Execute operation (AXIS)
MEM_ADDR_REG : starting memory address for AXIS read/write mode.
MEM_LEN_REG : number of samples to be transferred in AXIS read/write mode.
DMEM: The internal data memory is 2^DMEM_N samples, 32 bits each. The memory can be accessed either single read/write from AXI interface. The lower 256 Bytes are reserved for registers. The memory is then accessed in the upper section (beyond 256 bytes). Byte to sample conversion needs to be performed. The other method is to DMA in and out. Here the access is direct, so no conversion is needed. There is an arbiter to ensure data coherency and avoid blocking transactions.
- start()[source]
Start tProc from register. This has no effect if the tProc is not in init or end state, or if the start source is set to “external.”
- reset()[source]
Force the tProc to stop by filling the program memory with “end” instructions. For speed, we hard-code the “end” instruction and write directly to the program memory. This typically takes about 1 ms.
- reload_program()[source]
Write the most recently written program to the tProc program memory. This is normally useful after a reset (which erases the program memory)
- start_src(src)[source]
Sets the start source of tProc
- Parameters:
src (string) – start source “internal” or “external”
- class qick.drivers.tproc.Axis_QICK_Proc(*args: Any, **kwargs: Any)[source]
Bases:
SocIpAxis_QICK_Proc class
AXIS T_PROC xREG
TPROC_CTRL Write / Read 32-Bits TPROC_CFG Write / Read 32-Bits MEM_ADDR Write / Read 16-Bits MEM_LEN Write / Read 16-Bits MEM_DT_I Write / Read 32-Bits TPROC_W_DT1 Write / Read 32-Bits TPROC_W_DT2 Write / Read 32-Bits CORE_CFG Write / Read 32-Bits READ_SEL Write / Read 32-Bits MEM_DT_O Read Only 32-Bits TPROC_R_DT1 Read Only 32-Bits TPROC_R_DT2 Read Only 32-Bits TIME_USR Read Only 32-Bits TPROC_STATUS Read Only 32-Bits TPROC_DEBUG Read Only 32-Bits #################### TPROC_CTRL[0] - Time Reset : Reset absTimer TPROC_CTRL[1] - Time Update : Update absTimer TPROC_CTRL[2] - Proc Start : Reset and Starts tProc (Time and cores) TPROC_CTRL[3] - Proc Stop : Stop the tProc TPROC_CTRL[4] - Core Start : Reset and Starts the Cores. TPROC_CTRL[5] - Core Stop : Stop the Cores (Time will continue Running) TPROC_CTRL[6] - Proc Reset : Reset the TProc TPROC_CTRL[7] - Proc Run : Reset the TProc TPROC_CTRL[8] - Proc Pause : Pause the TProc (Time RUN, Core NO) TPROC_CTRL[9] - Proc Freeze : Freeze absTimer (Core RUN, Time no) TPROC_CTRL[10] - Proc Step : Debug - Step tProc(Time and CORE ) TPROC_CTRL[11] - Core Step : Debug - Step Core (Execute ONE instruction) TPROC_CTRL[12] - Time Step : Debug - Step Timer (Increase absTimer in 1) TPROC_CTRL[13] - COND_set : Set External Condition Flag from TPROC_CTRL[14] - COND_clear : Clears External Condition Flag from #################### TPROC_CFG[0] - MEM_START TPROC_CFG[1] - MEM_OPERATION TPROC_CFG[3:2] - MEM_TYPE (00-NONE, 01-PMEM, 10-DMEM, 11-WMEM) TPROC_CFG[4] - MEM_SOURCE (0-AXI, 1-SINGLE) TPROC_CFG[6:5] - MEM_BANK (TPROC, CORE0, CORE1) TPROC_CFG[10] - Disable INPUT CTRL TPROC_CFG[11] - WFIFO_Full Pause Core TPROC_CFG[12] - DFIFO_Full Pause Core
- param mem:
memory address
- type mem:
int
- param axi_dma:
axi_dma address
- type axi_dma:
int
- port2ch(portname)[source]
Translate a port name to a channel number and type Used in connection mapping.
- single_read(mem_sel, addr)[source]
Reads the bottom 32 bits of one sample of tProc memory using AXI access Do not use! Use the DMA instead.
- class qick.drivers.tproc.Axis_QICK_Net(*args: Any, **kwargs: Any)[source]
Bases:
SocIpAxis_QICK_Proc class
AXIS T_CORE xREG
CORE_CTRL Write / Read 32-Bits CORE_CFG Write / Read 32-Bits RAXI_DT1 Write / Read 32-Bits RAXI_DT2 Write / Read 32-Bits CORE_R_DT1 Read Only 32-Bits CORE_R_DT2 Read Only 32-Bits PORT_LSW Read Only 32-Bits PORT_MSW Read Only 32-Bits RAND Read Only 32-Bits CORE_W_DT1 Read Only 32-Bits CORE_W_DT2 Read Only 32-Bits CORE_STATUS Read Only 32-Bits CORE_DEBUG Read Only 32-Bits
- param mem:
memory address
- type mem:
int
- param axi_dma:
axi_dma address
- type axi_dma:
int