qick.drivers.readout

Drivers for readouts (FPGA blocks that receive data from ADCs) and buffers (blocks that receive data from readouts).

Classes

AbsPFBReadout(*args, **kwargs)
AbsReadout(iptype, fullpath)
AxisAvgBuffer(*args, **kwargs)	AxisAvgBuffer class
AxisBufferDdrV1(*args, **kwargs)	The DDR4 buffer block is similar to the decimated buffer in the avg_buffer block, except that data is written to DDR4 memory instead of FPGA memory.
AxisPFBReadoutV2(*args, **kwargs)	AxisPFBReadoutV2 class.
AxisPFBReadoutV3(*args, **kwargs)	AxisPFBReadoutV3 class.
AxisPFBReadoutV4(*args, **kwargs)	AxisPFBReadoutV4 class.
AxisReadoutV2(*args, **kwargs)	AxisReadoutV2 class
AxisReadoutV3(fullpath)	tProc-controlled readout block.
MrBufferEt(*args, **kwargs)

class qick.drivers.readout.AbsReadout(iptype, fullpath)

Bases: DummyIp

update()

Push the register values to the readout logic.

class qick.drivers.readout.AxisReadoutV2(*args: Any, **kwargs: Any)

Bases: SocIp, AbsReadout

AxisReadoutV2 class

Registers. FREQ_REG : 32-bit.

PHASE_REG : 32-bit.

NSAMP_REG : 16-bit.

OUTSEL_REG : 2-bit. * 0 : product. * 1 : dds. * 2 : input (bypass).

MODE_REG : 1-bit. * 0 : NSAMP. * 1 : Periodic.

WE_REG : enable/disable to perform register update.

Parameters:

fs (float) – sampling frequency in MHz

update()

Update register values

set_all_int(regs)

Set all readout parameters using a dictionary computed by QickConfig.calc_ro_regs().

set_all(f, sel='product', gen_ch=None, phase=0)

Set up the readout directly.

This method is not normally used, it’s only for debugging and testing. Normally the PFB is configured based on parameters supplied in QickProgram.declare_readout().

class qick.drivers.readout.AbsPFBReadout(*args: Any, **kwargs: Any)

Bases: SocIp, AbsReadout

set_ch(f, out_ch, sel='product', gen_ch=None, phase=0)

Set up a single PFB output.

This method is not normally used, it’s only for debugging and testing. Normally the PFB is configured based on parameters supplied in QickProgram.declare_readout().

class qick.drivers.readout.AxisPFBReadoutV2(*args: Any, **kwargs: Any)

Bases: AbsPFBReadout

AxisPFBReadoutV2 class.

This readout block contains a polyphase filter bank with 8 channels. Channel i mixes the input signal down by a fixed frequency f = i * fs/16, then by a programmable DDS with a range of +/- fs/16.

The PFB channels can be freely mapped to the 4 outputs of the readout block.

Registers. FREQ[0-7]_REG : 32-bit frequency of each channel.

OUTSEL_REG : 2-bit. * 0 : product. * 1 : input (bypass). * 2 : dds.

CH[0-3]SEL_REG : 3-bit ID mapping an output channel to an input.

set_out(sel='product')

Select readout signal output

Parameters:

sel (int) – select mux control

class qick.drivers.readout.AxisPFBReadoutV3(*args: Any, **kwargs: Any)

Bases: AbsPFBReadout

AxisPFBReadoutV3 class.

This readout block contains a polyphase filter bank with 64 channels. Channel i mixes the input signal down by a fixed frequency f = i * fs/64, then by a programmable DDS with a range of +/- fs/32.

The PFB channels can be freely mapped to the 4 outputs of the readout block.

DDS blocks are Phase-Coherent. The same PFB channel can be sent to multiple outputs.

For channel selection, channels are streamed out the PFB using TDM, with L=8 parallel channels each clock. The number of packets is N/L = 64/8 = 8. The IDx_REG should be mapped as follows:

• IDx_REGlower 8 bits are the “packet” field, from 0 .. 7 (N/L).

  : upper 8 bits are the “index” field, from 0 .. 7 (L-1).

There are 4 IDx_REG, one per selectable output.

Registers. ID[0-3]_REG : 16-bit channel selection. FREQ[0-3]_REG : 32-bit frequency of each output channel. PHASE[0-3]_REG : 32-bit phase of each output channel.

class qick.drivers.readout.AxisPFBReadoutV4(*args: Any, **kwargs: Any)

Bases: AxisPFBReadoutV3

AxisPFBReadoutV4 class.

This is identical to AxisPFBReadoutV3, but with 8 outputs instead of 4.

class qick.drivers.readout.AxisReadoutV3(fullpath)

Bases: AbsReadout

tProc-controlled readout block. This isn’t a PYNQ driver, since the block has no registers for PYNQ control. We still need this class to represent the block and its connectivity.

class qick.drivers.readout.AxisAvgBuffer(*args: Any, **kwargs: Any)

Bases: SocIp

AxisAvgBuffer class

Registers. AVG_START_REG * 0 : Averager Disabled. * 1 : Averager Enabled (started by external trigger).

AVG_ADDR_REG : start address to write results.

AVG_LEN_REG : number of samples to be added.

AVG_DR_START_REG * 0 : do not send any data. * 1 : send data using m0_axis.

AVG_DR_ADDR_REG : start address to read data.

AVG_DR_LEN_REG : number of samples to be read.

BUF_START_REG * 0 : Buffer Disabled. * 1 : Buffer Enabled (started by external trigger).

BUF_ADDR_REG : start address to write results.

BUF_LEN_REG : number of samples to be buffered.

BUF_DR_START_REG * 0 : do not send any data. * 1 : send data using m1_axis.

BUF_DR_ADDR_REG : start address to read data.

BUF_DR_LEN_REG : number of samples to be read.

Parameters:

• axi_dma_avg (str) – dma block for average buffers

• switch_avg (str) – switch block for average buffers

• axi_dma_buf (str) – dma block for raw buffers

• switch_buf (str) – switch block for raw buffers

• channel (int) – readout channel selection

set_freq(f, gen_ch=0)

Set the downconversion frequency on the readout that drvies this buffer.

Parameters:

• f (float) – frequency in MHz (before adding any DAC mixer frequency)

• gen_ch (int) – DAC channel (use None if you don’t want to round to a valid DAC frequency)

config(address=0, length=100)

Configure both average and raw buffers

Parameters:

• addr (int) – Start address of first capture

• length (int) – window size

enable()

Enable both average and raw buffers

config_avg(address=0, length=100)

Configure average buffer data from average and buffering readout block

Parameters:

• addr (int) – Start address of first capture

• length (int) – window size

transfer_avg(address=0, length=100)

Transfer average buffer data from average and buffering readout block.

Parameters:

• addr (int) – starting reading address

• length (int) – number of samples

Returns:

I,Q pairs

Return type:

list

enable_avg()

Enable average buffer capture

disable_avg()

Disable average buffer capture

config_buf(address=0, length=100)

Configure raw buffer data from average and buffering readout block

Parameters:

• addr (int) – Start address of first capture

• length (int) – window size

transfer_buf(address=0, length=100)

Transfer raw buffer data from average and buffering readout block

Parameters:

• addr (int) – starting reading address

• length (int) – number of samples

Returns:

I,Q pairs

Return type:

list

enable_buf()

Enable raw buffer capture

disable_buf()

Disable raw buffer capture

class qick.drivers.readout.MrBufferEt(*args: Any, **kwargs: Any)

Bases: SocIp

class qick.drivers.readout.AxisBufferDdrV1(*args: Any, **kwargs: Any)

Bases: SocIp

The DDR4 buffer block is similar to the decimated buffer in the avg_buffer block, except that data is written to DDR4 memory instead of FPGA memory.

Typically multiple readouts will be connected to this buffer through a switch. The driver assumes that input(s) to this buffer are also sent to avg_buffer blocks.

wlen(len_=10)

Set the number of bursts. Each burst is 256 IQ pairs.