qick.qick

The lower-level driver for the QICK library. Contains classes for interfacing with the SoC.

Functions

format_buffer(buff)

Return the I and Q values associated with a buffer value.

Classes

`AxisAvgBuffer`(ip, axi_dma_avg, switch_avg, ...)	AxisAvgBuffer class
`AxisReadoutV2`(ip, fs, **kwargs)	AxisReadoutV2 class
`AxisSignalGenV4`(ip, axi_dma, axis_switch, ...)	AxisSignalGenV4 class
`AxisSwitch`(ip[, nslave, nmaster])	AxisSwitch class to control Xilinx AXI-Stream switch IP
`AxisTProc64x32_x8`(ip, mem, axi_dma)	AxisTProc64x32_x8 class
`QickSoc`(args, *kwargs)	QickSoc class.
`SocIp`(ip, **kwargs)	SocIp class

qick.qick.format_buffer(buff)[source]

Return the I and Q values associated with a buffer value. The lower 16 bits correspond to the I value, and the upper 16 bits correspond to the Q value.

Parameters: buff (int) – Buffer location
Returns

dataI (int) - I data value
dataQ (int) - Q data value

class qick.qick.SocIp(ip, **kwargs)[source]

Bases: object

SocIp class

write(offset, s)[source]

Writes a value s to a register specified by an offset value

Parameters

offset (int) – Offset value (register)
s (int) – value to be written

read(offset)[source]

Reads an offset

Parameters: offset (int) – Offset value

class qick.qick.AxisSignalGenV4(ip, axi_dma, axis_switch, channel, **kwargs)[source]

Bases: qick.qick.SocIp

AxisSignalGenV4 class

AXIS Signal Generator V4 Registers. START_ADDR_REG

WE_REG * 0 : disable writes. * 1 : enable writes.

load(xin_i, xin_q, addr=0)[source]

Load waveform into I,Q envelope

Parameters

xin_i (list) – real part of envelope
xin_q (list) – imaginary part of envelope
addr (int) – starting address

wr_enable(addr=0)[source]: Enable WE reg

wr_disable()[source]: Disable WE reg

rndq(sel_)[source]: TODO: remove this function. This functionality was removed from IP block.

class qick.qick.AxisReadoutV2(ip, fs, **kwargs)[source]

Bases: qick.qick.SocIp

AxisReadoutV2 class

Registers. FREQ_REG : 32-bit.

PHASE_REG : 32-bit.

NSAMP_REG : 16-bit.

OUTSEL_REG : 2-bit. * 0 : product. * 1 : dds. * 2 : bypass.

MODE_REG : 1-bit. * 0 : NSAMP. * 1 : Periodic.

WE_REG : enable/disable to perform register update.

Parameters

ip (str) – IP address
fs (float) – sampling frequency in MHz

update()[source]: Update register values

set_out(sel='product')[source]

Select readout signal output

Parameters: sel (int) – select mux control

set_freq(f)[source]

Set frequency register

Parameters: f (float) – frequency in MHz

set_freq_int(f_int)[source]

Set frequency register (integer version)

Parameters: f_int (int) – frequency value register

class qick.qick.AxisAvgBuffer(ip, axi_dma_avg, switch_avg, axi_dma_buf, switch_buf, channel, **kwargs)[source]

Bases: qick.qick.SocIp

AxisAvgBuffer class

Registers. AVG_START_REG * 0 : Averager Disabled. * 1 : Averager Enabled (started by external trigger).

AVG_ADDR_REG : start address to write results.

AVG_LEN_REG : number of samples to be added.

AVG_DR_START_REG * 0 : do not send any data. * 1 : send data using m0_axis.

AVG_DR_ADDR_REG : start address to read data.

AVG_DR_LEN_REG : number of samples to be read.

BUF_START_REG * 0 : Buffer Disabled. * 1 : Buffer Enabled (started by external trigger).

BUF_ADDR_REG : start address to write results.

BUF_LEN_REG : number of samples to be buffered.

BUF_DR_START_REG * 0 : do not send any data. * 1 : send data using m1_axis.

BUF_DR_ADDR_REG : start address to read data.

BUF_DR_LEN_REG : number of samples to be read.

Parameters

ip (str) – IP address
axi_dma_avg (str) – dma block for average buffers
switch_avg (str) – switch block for average buffers
axi_dma_buf (str) – dma block for raw buffers
switch_buf (str) – switch block for raw buffers
channel (int) – readout channel selection

config(address=0, length=100)[source]

Configure both average and raw buffers

Parameters

addr (int) – Start address of first capture
length (int) – window size

enable()[source]: Enable both average and raw buffers

config_avg(address=0, length=100)[source]

Configure average buffer data from average and buffering readout block

Parameters

addr (int) – Start address of first capture
length (int) – window size

transfer_avg(buff, address=0, length=100)[source]

Transfer average buffer data from average and buffering readout block

Parameters

buff (list) – DMA buffer to be used for transfer
addr (int) – starting reading address
length (int) – number of samples

Returns

I,Q pairs

Return type

list

enable_avg()[source]: Enable average buffer capture

disable_avg()[source]: Disable average buffer capture

config_buf(address=0, length=100)[source]

Configure raw buffer data from average and buffering readout block

Parameters

addr (int) – Start address of first capture
length (int) – window size

transfer_buf(buff, address=0, length=100)[source]

Transfer raw buffer data from average and buffering readout block

Parameters

buff (list) – DMA buffer to be used for transfer
addr (int) – starting reading address
length (int) – number of samples

Returns

I,Q pairs

Return type

list

enable_buf()[source]: Enable raw buffer capture

disable_buf()[source]: Disable raw buffer capture

class qick.qick.AxisTProc64x32_x8(ip, mem, axi_dma)[source]

Bases: qick.qick.SocIp

AxisTProc64x32_x8 class

AXIS tProcessor registers: START_SRC_REG * 0 : internal start. * 1 : external start.

START_REG * 0 : stop. * 1 : start.

MEM_MODE_REG * 0 : AXIS Read (from memory to m0_axis) * 1 : AXIS Write (from s0_axis to memory)

MEM_START_REG * 0 : Stop. * 1 : Execute operation (AXIS)

MEM_ADDR_REG : starting memory address for AXIS read/write mode.

MEM_LEN_REG : number of samples to be transferred in AXIS read/write mode.

DMEM: The internal data memory is 2^DMEM_N samples, 32 bits each. The memory can be accessed either single read/write from AXI interface. The lower 256 Bytes are reserved for registers. The memory is then accessed in the upper section (beyond 256 bytes). Byte to sample conversion needs to be performed. The other method is to DMA in and out. Here the access is direct, so no conversion is needed. There is an arbiter to ensure data coherency and avoid blocking transactions.

Parameters

ip (str) – IP address
mem (int) – memory address
axi_dma (int) – axi_dma address

start_src(src=0)[source]

Sets the start source of tProc

Parameters: src (int) – start source

start()[source]: Start tProc from register

stop()[source]: Stop tProc from register

load_qick_program(prog, debug=False)[source]

Parameters

prog (str) – the QickProgram to load
debug (bool) – Debug option

load_program(prog='prog.asm', fmt='asm')[source]

Loads tProc program. If asm progam, it compiles first

Parameters

prog (string) – program file name
fmt (string) – file format

single_read(addr)[source]

Reads one sample of tProc data memory using AXI access

Parameters

addr (int) – reading address
data (int) – value to be written

Returns

requested value

Return type

int

single_write(addr=0, data=0)[source]

Writes one sample of tProc data memory using AXI access

Parameters

addr (int) – writing address
data (int) – value to be written

load_dmem(buff_in, addr=0)[source]

Writes tProc data memory using DMA

Parameters

buff_in (int) – Input buffer
addr (int) – Starting destination address

read_dmem(addr=0, length=100)[source]

Reads tProc data memory using DMA

Parameters

addr (int) – Starting address
length (int) – Number of samples

Returns

List of memory data

Return type

list

class qick.qick.AxisSwitch(ip, nslave=1, nmaster=4, **kwargs)[source]

Bases: qick.qick.SocIp

AxisSwitch class to control Xilinx AXI-Stream switch IP

Parameters

ip (str) – IP address
nslave (int) – Number of slave interfaces
nmaster (int) – Number of master interfaces

disable_ports()[source]: Disables ports

sel(mst=0, slv=0)[source]

Digitally connects a master interface with a slave interface

Parameters

mst (int) – Master interface
slv (int) – Slave interface

class qick.qick.QickSoc(*args: Any, **kwargs: Any)[source]

Bases: pynq.Overlay

QickSoc class. This class will create all object to access system blocks

Parameters

bitfile (str) – Name of the bitfile
force_init_clks (bool) – Whether the board clocks are re-initialized
ignore_version (bool) – Whether version discrepancies between PYNQ build and firmware build are ignored

set_all_clks()[source]: Resets all the board clocks

get_decimated(ch, address=0, length=1024)[source]

Acquires data from the readout decimated buffer

Parameters

ch (int) – ADC channel
address (int) – Address of data
length (int) – Buffer transfer length

Returns

List of I and Q decimated arrays

Return type

list

get_accumulated(ch, address=0, length=16384)[source]

Acquires data from the readout accumulated buffer

Parameters

ch (int) – ADC channel
address (int) – Address of data
length (int) – Buffer transfer length

Returns

di[:length] (list) - list of accumulated I data
dq[:length] (list) - list of accumulated Q data

set_nyquist(ch, nqz)[source]

Sets DAC channel ch to operate in Nyquist zone nqz mode

Channel 1 : connected to Signal Generator V4, which drives DAC 228 CH0. Channel 2 : connected to Signal Generator V4, which drives DAC 228 CH1. Channel 3 : connected to Signal Generator V4, which drives DAC 228 CH2. Channel 4 : connected to Signal Generator V4, which drives DAC 229 CH0. Channel 5 : connected to Signal Generator V4, which drives DAC 229 CH1. Channel 6 : connected to Signal Generator V4, which drives DAC 229 CH2. Channel 7 : connected to Signal Generator V4, which drives DAC 229 CH3. tiles: DAC 228: 0, DAC 229: 1 channels: CH0: 0, CH1: 1, CH2: 2, CH3: 3

Parameters

ch (int) – DAC channel
nqz (int) – Nyquist zone

Returns

‘True’ or ‘1’ if the task was completed successfully

Return type

bool